p-채널 Poly-Si TFT s 소자의 Hot-Carrier 효과에 관한 연구

A Study on the Hot-Carrier Effects of p-Channel Poly-Si TFT s

  • 진교원 (수원대학교 전자재료공학과) ;
  • 박태성 (수원대학교 전자재료공학과) ;
  • 백희원 (수원대학교 전자재료공학과) ;
  • 이진민 (수원대학교 전자재료공학과) ;
  • 조봉희 (수원대학교 전기전자정보통신 공학부) ;
  • 김영호 (수원대학교 전자재료공학과)
  • 발행 : 1998.09.01

초록

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

키워드

참고문헌

  1. IEE Proc.-Circuit Devices Syst. no.141 Aryes, J. R.;Young, N. D.
  2. IEEE Electron Device Lett. v.11 no.4 Mechanism of device degradation in n- and p-Channel polysilicon TFT's by electrical stressing Wu, I. -W.;Jackson, W. B.;Huang, T. -Y.;Lewis, A. G.;Chiang, A.
  3. Semicond. Sci. Technol. v.5 Electron trapping instabilities in polycrystalline silicon thin-film transistors Young, N. D.;Grill, A.