전자공학회논문지D (Journal of the Korean Institute of Telematics and Electronics D)
- 제35D권1호
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- Pages.41-48
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- 1998
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- 1226-5845(pISSN)
SUM 선택신호 발생 방식을 이용한 64-bit 가산기의 설계
Sum-selector generation algorithm based 64-bit adder design
초록
This paper proposes a new addition algorithm to improve the addition speed which is one of the important factors for data path functions. We have designed a fast 64-bit adder utilizing al dynamic chain architecture based on the proposed Sum-Selector Generation (SSG) algorithm. Proposed adder is designed with pass-transistor logicto achieve a high speed operation in low voltage circumstance. Realized 64-bit adder with 0.8.mu.m CMOS double-metal process technology has been fully tested. it operates at 185 MHz with 5.0V and chip area occupies 3.66mm
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