Journal of the Korean Institute of Telematics and Electronics C (전자공학회논문지C)
- Volume 35C Issue 1
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- Pages.10-14
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- 1998
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- 1226-5853(pISSN)
Design of a fast double edge traiggered D-tyupe flip-flop
고속 듀얼 모서리 천이 D형 플립-플롭의 설계
Abstract
In this paper a double edge triggered (DET) filp-flop is proposed which changes its output state at both the positive and the negative edge transitions of the triggering input. DET filp-flop has advantages in terms of speed and power dissipation over single edge triggered (SET) filp-flop has proposed DET flip-flop needs only 12 MOS transistors and can operate at clock speed of 500 MHz. Also, the power dissipation has decreased about 33% in comparison to SET flip-flop.
Keywords