Journal of the Korean Institute of Telematics and Electronics C (전자공학회논문지C)
- Volume 35C Issue 8
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- Pages.23-32
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- 1998
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- 1226-5853(pISSN)
Design of a memory compiler for ASIC
ASIC용 메모리 컴파일러 설계
Abstract
In this paper, we propose a memory compiler to genrate embedded RAMs and ROMs for ASIC chips. We design the leaf cells to be compsoed of memory blocks. The compiler is built using tile-based method to simplify routing. The compiler can genrate any memory layouts to satisfy 64 to 4096 words and 4 to 256 bits per word. The technology we used here is 0.8.mu.m single poly double metal CMOS process. The address access time and power consumption are verifie dthrough the HSPICE simulation.
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