References
- A Small-Area, High Speed, Threshold-Voltage-Mismatch Compensation Sense Amplifier for Gb-Scale DRAM Arrays Proc. ESSCIRC Kawahara, T.(et al.)
- A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierachical Square-Shaped Memory Block and Distributed Bank Architecture ISSCC Nitta, Y.(et al.)
- A 32-Bank 1Gb DRAM WITH 1GB/s Bandwidth ISSCC Yoo, J.(et al.)
- Process Innovation for Future Semiconductor Industry VLSI Tech. Ogirima. M.
- DRAM Technology for Gigabit Age SSDM Takada, M.
- IEDM, SSDM, VLSI, 및 ISSCC 1993~1996참조
- NIKKEI MICRODEVICES 1995년 7월, Semiconductor International 1995년 1월, 반도체산업 1996년 1,6월 참조