Design of a cosynthesis system for pipelined application-specific instruction processors

파이프라인을 지원하는 ASIP 합성 시스템의 설계

  • 현민호 (서강대학교 전자공학과) ;
  • 이석근 (삼성항공 정밀기기 연구소) ;
  • 박창욱 (서두로직 종합기술연구소) ;
  • 황선영 (서강대학교 전자공학과)
  • Published : 1997.03.01

Abstract

This paper presents the prototype design of hardware/software cosynthesis system for pipelined application-specific instruction processors. Taking application programs in VHDL as inputs, the proposed system generates a pipelined instruction-set processor and the instruction sequences running on the generated machine. The design space of datapath and controller is defined by the architectural templates embedded in the system. Generating the intyermediate code adequate for parallelism analysis and extraction, the system converts it into assembly codes. Experimental results show the effectiveness of the proposed system.

Keywords

References

  1. Proceedings of the IEEE v.82 no.7 Hardware-Software Co-Design of Embedded System W. Wolf
  2. in Proc. Int'l Conf. on CAD Register Assignment through Resource Classification for ASIP Microcode Generation C. Liem;T. May;P. Paulin
  3. in Proc. Int'l Conf. on CAD Generating Instruction Sets and Microarchitectures from Application I. Huang;A. Despain
  4. in Proc. Int'I Conf. on CAD Design of System-Level Modules J. Sun;R. Brodersen
  5. in Proc. Int'I Conf. on CAD A Partitioning Algorithm for System-Level Synthesis G. Menez;R. Ortega
  6. in Proc. Int'I Conf. on CAD Instruction Set Mapping for Performance Optimization M. Corazao;M. Khalaf
  7. in Proc. Int'I Conf. on CAD An ASIP Instruction Set Optimization Algorithm with fuctional Module Sharing Constraint A. Alomary;T. Nakata
  8. in Proc. Int'I Conf. on CAD Hardware/Software Resolution of Pipeline Synthesis of Instruction Set Processors I. Huang;A. Despain
  9. High Level Synthesis of ASICs under Timing and Synchronization Constraints D. Ku;G. De Micheli
  10. Reduced Instruction Set Computer Architectures for VLSI M. Katevenis
  11. MIPS R2000 RISC Architecture G. Kane
  12. The Advanced Intel Microprocessors B. Brey
  13. Computer Architecture and Design A. van de Goor
  14. IEEE Trans. on CAD/ICAS v.CAD-8 no.6 Force-Directed Scheduling for the Behavioral Synthesis of ASIC's P. Paulin;J. Knight
  15. Computer Architecture B. Wilkinson
  16. Advanced Computer Architecture K. Hwang
  17. Technical Report CSL-86-289 MIPS-X Instruction Set and Programmer's Manual P. Chow
  18. Microprocessor Report v.6 no.14 SPARC Hits Low End with TI's micro SPARC B. Case