The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Design of a cosynthesis system for pipelined application-specific instruction processors

파이프라인을 지원하는 ASIP 합성 시스템의 설계

  • 현민호 (서강대학교 전자공학과) ;
  • 이석근 (삼성항공 정밀기기 연구소) ;
  • 박창욱 (서두로직 종합기술연구소) ;
  • 황선영 (서강대학교 전자공학과)
  • Published : 1997.03.01
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Abstract

This paper presents the prototype design of hardware/software cosynthesis system for pipelined application-specific instruction processors. Taking application programs in VHDL as inputs, the proposed system generates a pipelined instruction-set processor and the instruction sequences running on the generated machine. The design space of datapath and controller is defined by the architectural templates embedded in the system. Generating the intyermediate code adequate for parallelism analysis and extraction, the system converts it into assembly codes. Experimental results show the effectiveness of the proposed system.

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References

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