An Amorphous Silicon Local Interconnection (ASLI) CMOS with Self-Aligned Source/Drain and Its Electrical Characteristics

  • Published : 1997.12.31

Abstract

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

Keywords

References

  1. J. Solid-State Circ. v.SC-9 no.5 Design of ion-implanted MOSFET's with very small physical dimensions Dennard, R.H.;Gaensslen, F.H.;Yu, H.N.;Rideout, V.L.;Bassous, E.;LeBlanc, A.R.
  2. Microelectronics and Reliability v.37 Scaling down and reliability problems of gigabit CMOS circuits Krautschneider, W.H.;Kohlhase, A.;Terletzki, H.
  3. IEEE Electron Device Lett. v.42 Short channel effect suppressed sub-0.1-${\mu}m$ grooved-gate MOSFET's with W gate Kimura, S.;Tanaka, J.;Noda, H.;Toyabe, T.;Ihara, S.
  4. IEEE Trans. Electron Devices v.43 no.8 Short-channel effect immunity and current capability of sub-0.1-micron MOSFET's using a recessed channel Bricout, P.H.;Dubois, E
  5. Tech. Dig. IEEE Int's Electron Devices Meeting A 0.1 ${\mu}m$-gate elevated source and drain MOSFET fabricated by phase-shifted lithography Kimura, S.;Noda, H.;Hisamoto, D.;Takeda, E.
  6. Tech. Dig. IEEE Int'l Electron Devices Meeting Threshold voltage controlled 0.1-${\mu}m$ MOSFET utilizing inversion layer as extreme shallow source/drain Noda, H.;Murai, F.;Kimura, S.
  7. Symp. on VLSI Tech. High performance 0.1-${\mu}m$ room temperature Si MOSFET's Yan, R.H.;Lee, K.F.;Jeon, D.J.;Kim, Y.O.;Park, B.G.;Pinto, M.R.;Rafferty, C.S.;Tennant, D.M.;Westerwick, E.H.;Chin, G.M.;Morris, M.C.;Early, K.;Mulgrew, P.;Mansfield, W.M.;Watts, R.K.;Vashchenkov, A.M.;Swartz, R.G.;Ourmazd, A.
  8. Symp. on VLSI Technology The use of rapid thermal processing to improve performance of sub- half micron CMOS with and without salicide Chapman, R.A.;Rodder, M.;Moslehi, M.M.;Velo, L.;Kuehne, J.W.;Lane, A.P.
  9. Tech. Dig. IEEE Int'l Electron Device Meeting A 0.05 ${\mu}m$ CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing Hori, A.;Nakaoka, H.;Umimoto, H.;Yamashita, K.;Takase, M.;Shimizu, N.;Mizuno, B.;Odanaka, S.
  10. Tech. Dig. IEEE Int'l Electron Device Meeting Sub-50 nm gate length N-MOSFETS with 10 nm phosphorous source and drain junctions Ono, M.;Saito, M.;Yoshitomi, T.;Fiegna, C.;Ohguro, T.;Iwai, H.
  11. Symp. on VLSI Tech. Novel deep sub-quarter micron PMOSFETs with ultra-shallow junctions utilizing boron diffusion from poly-Si/Oxide (BDSOX) Togo, M.;Mogami, T.;Uwasawa, K.;Kunio, T.
  12. IEEE Trans. Electron Devices v.43 no.7 A self-aligned counter-doped well process utilizing channel ion implantation Nakamura, H.;Horiuchi, T.
  13. Electronics Lett. v.33 no.5 CMOS device with self-aligned source/drain using amorphous silicon local interconnection layer Yoon, Y.S.;Baek, K.H.;Nam, K.S.
  14. IEEE Trans. Electron Devices v.43 no.3 Characteristics of buried-channel pMOS devices with shallow counter-doped layers fabricated using channel preamorphization Miyake, M.;Okazaki, Y.;Kobayashi, T.