Batch Sizing Heuristic for Batch Processing Workstations in Semiconductor Manufacturing

반도체 생산 배취공정에서의 배취 크기의 결정

Semiconductor manufacturing line includes several batch processes which are to be controlled effectively to enhance the productivity of the line. The key problem in batch processes is a dynamic batch sizing problem which determines number of lots processed simultaneously in a single botch. The batch sizing problem in semiconductor manufacturing has to consider delay of lots, setup cost of the process, machine utilization and so on. However, an optimal solution cannot be attainable due to dynamic arrival pattern of lots, and difficulties in forecasting future arrival times of lots of the process. This paper proposes an efficient batch sizing heuristic, which considers delay cost, setup cost, and effect of the forecast errors in determining the botch size dynamically. Extensive numerical experiments through simulation are carried out to investigate the effectiveness of the proposed heuristic in four key performance criteria: average delay, variance of delay, overage lot size and total cost. The results show that the proposed heuristic works effectively and efficiently.