SCF를 이용한 시간지연 회로의 설계 및 제작기술 개발

Developement of Designing and Manufacturing Technique for Time Delay Circuit using SCF.

This paper deals with the tapped time delay circuit with SCF(Switched Capacitor Filters). This filter is composed of lossless discrete integrator and the SCF has 2-phase clocks. Experimental results have shown that telephone signals (0~4kHz) could be delayed in the range of sampling frequency 80kHz. But above the range, operational amplifiers and analog switchs have been difficult in the normal operating condition.