Acknowledgement
Supported by : 산학협동재단
Journal of Industrial Technology (산업기술연구)
- Volume 16
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- Pages.191-195
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- 1996
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- 1229-9588(pISSN)
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- 1598-1371(eISSN)
Developement of Designing and Manufacturing Technique for Time Delay Circuit using SCF.
SCF를 이용한 시간지연 회로의 설계 및 제작기술 개발
- Published : 1996.10.31
Abstract
This paper deals with the tapped time delay circuit with SCF(Switched Capacitor Filters). This filter is composed of lossless discrete integrator and the SCF has 2-phase clocks. Experimental results have shown that telephone signals (0~4kHz) could be delayed in the range of sampling frequency 80kHz. But above the range, operational amplifiers and analog switchs have been difficult in the normal operating condition.
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