Design of a high-precision MOSFET threshold voltage extractor

고정밀 MOSFET 문턱전압 추출회로 설계

A threshold voltage extraction scheme which does not need matched replica of the MOSFET under test is proposed. In contrast to alternative methods, the accuracy of the proposed scheme does not depend on the matching of the test transistors. The proposed scheme has been implemented in a matching-free way using a switched-capacitor subtracting ampliier and a dynmic current mirror. Nonideal effects associated with these circuits, such as non-zero offset voltages and finite gains of op-amps, capcitor mismateches, and charge injection of MOS switches, are investigated and compensated. The circuit has been designed using ISRC 1.5.mu.m CMOS process parameters andfabricated at Inter-University semiconductor Research Center, and its performance has been evaluated.