전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제33A권3호
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- Pages.187-195
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- 1996
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- 1016-135X(pISSN)
새로운 동적 CMOS 논리 설계방식을 이용한 고성능 32비트 가산기 설계
Design of a high-speed 32-bit adder using a new dynamic CMOS logic
초록
This paper proposes two new dynamic CMOS logic styles, called ZMODL (zipper-MODL) and EZMODL (enhanced-ZMODL), which can reduce more area dnd propagation delya than conventional MODL (multiple output domino logic). The 32-bit CLAs(carry look-ahead adder) are designed by ZMODL, EZMODL circuits, and their operations are verified by SPICE 3 with 2
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