Communications of the Korean Institute of Information Scientists and Engineers (정보과학회지)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

Systolic Array의 설계

  • Published : 1995.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

Keywords

References

  1. International Conf. on Parallel Processing Efficient Mapping for Multidimensional systolic Arrays using Flexible buffer Structures Augustine,F.;Varadarajan,R.
  2. Journal of parallel and distributed computing v.7 The SDEF programming system Bradlley,R.E.;Cappello,P.R.
  3. Proc. of 2nd International Symp. on VLSI Technology, Systems, and Applications Synthesizing Systolic Designs Chen,M.C.
  4. IEEE international Conf. on ASSP Matrix Methods for the Design and Analysis of Recurrent Algorithms for Muti-Purpose Systolic Arrays Dowling,E.M.;Taylor,F.J.
  5. Computer v.20 no.7 Systolic Array-from Concept to Implementation Fortes,J.A.B.;Wah,B.W.
  6. Proc. of International Conf. on Parallel Processing Systemetic Approaches to the Design of Algorithmically Specified Systolic Arrays Fortes,J.A.B.;Fu,K.S.;Wah,B.W.
  7. International Conf. on Systolic Arrays A CHDL-Based CAD System for The Synthesis of Systolic Architecture Hartenstein,R.W.;Lemmert,K.
  8. Motif Programming Mannual Heller,D.
  9. Journal of ACM v.14 no.3 The organization of computations for uniform recurrence equations Karp,R.M.;Miller,R.E.;Winograd,S.
  10. Proc. of International conf. on Parallel Processing Optimal Designs of Linear Flow Systolic Architectures Kothari,S.C.;Gannett,E.;Oh,H.
  11. Workshop on Interconnection Networks for Parallel and Distributed processing Transforming algorithms for single-stage and VLSI architectures Kuhn,R.H.
  12. Sparse Matrix Proceedings SIAM Systolic Arrays(for VLSI) Kung,H.T.;Leiserson,C.E.
  13. IEEE Computer v.15 no.1 Why systolic architectures? Kung,H.T.
  14. CALTECH Conf. on VLSI Let's Design Algorithms for VLSI Systems Kung,H.T.
  15. VLSI Array Processors Kung,S.Y.
  16. VLSI Signal Processing III A VLSI Array Compiler System(VACS) for Array Design Kung,S.Y.;Jean,S.N.
  17. IEEE Trans. on Computers v.37 no.12 Synthesizing Linear Array Algorithms from Nested For Loop Algorithms Lee,P.;Kedem,Z.M.
  18. IEEE Trans. on parallel and distributed systems v.1 no.1 Mapping Nested Loop algorithms into MultiDimensional Systolic Arrays Lee,P.;Kedem,Z.M.
  19. IEEE Trans. on Computers v.c-34 no.1 The Design of Optimal Systolic Arrays Li,G.J.;Wah,B.W.
  20. Computing v.32 Spacetime representations of computational structures Miranker,W.L.;Winkler,A.
  21. IEEE Trans. on Computers v.C-31 On the Analysis and Synthesis of VLSI algorithms Moldovan,D.I.
  22. Proc. of The IEEE v.71 On the design of algorithms for VLSI systolic arrays Moldovan,D.I.
  23. IEEE Trans. Computer-Aided Design v.CAD-6 ADVIS: A Software package for the design of systolic arrays Moldovan,D.I.
  24. Proc. of 11th Annual Symp. on Computer Architecture Automatic synthesis of systolic arrays from Uniform Recurrent Equations Quinton,P.
  25. Ph. D. thesis, Stanford University Regular Iterative Algorithm and Their Implementations on Processor Arrays Rao,S.K.
  26. SPIE, Highly Parallel Signal Processing Architectures v.614 What is a Systolic Algorithm? Rao,S.K.;Kaiath,T.
  27. IEEE Trans. on Parallel and Distributed Systems v.3 no.3 On Time Mapping of Uniform DePendence Algorithms into Lower Dimensional Processor Arrays Shang,W.;Fortes,J.A.B.
  28. Computational Aspects of VLSI Ulman,J.D.
  29. PH. D. thesis, Rensselaer Polytechnic Institute A Systolic Array Design Methodology for Sequential Loop Algorithms Yoo,K.Y.
  30. VLSI Signal Processing IV Bounds on the number of linear allocation function Zhong,X.;Wong,I.;Rajopadhye,S.V.