이차원 Constant Geometry FFT VLSI 알고리즘 및 아키텍쳐

VLSI Algorithms & Architectures for Two Dimensional Constant Geometry FFT

A two dimensional constant geometry FFT algorithms and architectures with shuffled inputs and normally ordered outputs are presented. It is suitable for VLSI implementation because all buterfly stages have identical, regular structure. Also a methodology using shuffled FFT inputs and outputs to halve the number of butterfly stages connected by a global interconnection which requires much area is presented. These algorithms can be obtained by shuffling the row and column of a decomposed FFT matrix which corresponds to one butterfly stage. Using non-recursive and recursive pipeline, the degree of serialism and parallelism in FFT computation can be adjusted. To implement high performance high radix FFT easily and reduce the amount of interconnections between stages, the method to build a high radix PE with lower radix PE 's is discussed. Finally the performances of the present architectures are evaluated and compared.