전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제31A권3호
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- Pages.68-76
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- 1994
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- 1016-135X(pISSN)
CMOS 디지틀 설계를 위한 트랜지스터 크기의 최적화기법
New Transistor Sizing Algorithms For CMOS Digital Designs
초록
In the automatic transistor sizing with computer for optimizing delay and the chip area of CMOS digital circuits, conventionally either a mathematical method or a heuristic method has been used. In this paper, we present a new method of transistor sizing, a sort of combination of the above two methods, in which the mathematical method is used for sizing of critical paths and the heuristic method is used for desizing of non-critical paths. In order to reduce the overall problem dimension, a basic block called an extended stage is introduced which includes a basic stage, parallel transistors and complementary part. Optimization for multiple critical paths is formulated as a problem of area minimization subject to delay constraints and is solved by the augmented Lagrange multiplier method. The transistor sizes along non-critical paths are decreased successively without affecting the critical path delay times. The proposed scheme was successfully applied to several test circuits.
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