Journal of the Korean Institute of Telematics and Electronics B (전자공학회논문지B)
- Volume 30B Issue 10
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- Pages.1-12
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- 1993
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- 1016-135X(pISSN)
A Study on Hybrid Image Coder Using a Reconfigurable Multiprocessor System (Study I : H/W Implementation)
재구성 가능한 다중 프로세서 시스템을 이용한 혼합 영상 보호화기 구현에 관한 연구 (연구 I : H/W구현)
Abstract
A multiprocessor system for high-speed processing of hybrid image coding algorithms such as H.261, MPEG, or Digital HDTV is presented in this study. Using a combination of highly parallel 32-bit microprocessor, DCT(Discrete Cosine Transform), and motion detection processor, a new processing module is designed for the implementation of high performance coding system. The sysyem is implemented to allow parallel processing since a single module alone cannot perform hybrid coding algorithms at high speed, and crossbar switch is used to realize various parallel processing architectures by altering interconnections between processing modules within the system.
Keywords