전자공학회논문지B (Journal of the Korean Institute of Telematics and Electronics B)
- 제30B권2호
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- Pages.44-50
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- 1993
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- 1016-135X(pISSN)
영어 수계를 이용한 디지털 신경망회로의 실현
An Implementation of Digital Neural Network Using Systolic Array Processor
초록
In this paper, we will present an array processor for implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This operation procedure is suited for the design of an array processor, because it can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and compute sigmoid function. The proposed design method would expect to adopt for the application field of neural networks, because it can be realized to currently developed VLSI technology.
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