고주파수 동기장치용 DP-PLL의 설계를 위한 위상차 검출방식과 프로세스 알고리듬

A Phase-Difference Detection Method and its process Algorithm for DP-PLL Design of the High Frequency Synchronization Device

This paper describes a new phase-difference detection method and the associate process algorithm for calculating the mean value of phase difference detected and OVCXO control value and for monitoring and controlling the DP-PLL operation status to be used in the design of a high-frequency DP-PLL. Through the experiments of DP-PLL implemented with 16-bit processor, memories, pheriperals and OVCXO to eraluate the suggested method and algorithm, it is shown that a remarkable improvement in PLL function such as phase detection, and reference clock tracing capability, jitter absorbability and frequency stability compared with other existing DP-PLL synchronization device is achieved.