대한전자공학회논문지 (Journal of the Korean Institute of Telematics and Electronics)
- 제27권7호
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- Pages.1118-1127
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- 1990
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- 1016-135X(pISSN)
domino CMOS 논리회로의 테스트 생성에 관한 연구
A Study on Test Generation for Domino CMOS Logic Circuits
초록
In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.
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