대한산업공학회지 (Journal of Korean Institute of Industrial Engineers)
- 제14권1호
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- Pages.1-15
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- 1988
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- 1225-0988(pISSN)
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- 2234-6457(eISSN)
An Evaluation of Error Performance Estimation Schemes for DS1 Transmission Systems Carrying Live Traffic
초록
DS1 transmission systems use framing bit errors, bipolar violations and code-detected errors to estimate the bit error rate when determining errored and severely errored seconds. Using the coefficient of variation under the memoryless binary symmetric channel assumption, a basic framework to evaluate these estimation schemes is proposed to provide a practical guideline in determining errored and severely errored seconds which are fundamental in monitoring the real-ime error performance of DS1 transmission systems carrying live traffic. To evaluate the performance of the cyclic redundancy check code (CRC), a computer simulation model is used. Several drawbacks of the superframe format in association with real time error performance monitoring are discussed. A few recommendations are suggested in measuring errored and severely errored seconds, and determining service limit alarms through the use of the superframe format. Furthermore, we propose a new robust scheme for determining service limit alarms which take into consideration the limitations of some estimation schemes for the time interval of one second.
키워드