대한전자공학회논문지 (Journal of the Korean Institute of Telematics and Electronics)
- 제25권8호
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- Pages.937-949
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- 1988
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- 1016-135X(pISSN)
RISC 파이프라인 아키텍춰의 코드 최적화 알고리듬
A Code Optimization Algorithm of RISC Pipelined Architecture
초록
This paper proposes a code optimization algorithm for dealing with hazards which are occurred in pipelined architecture due to resource dependence between executed instructions. This algorithm solves timing hazard which results from resource conflict between concurrently executing instructions, and sequencing hazard due to the delay time for branch target decision by reconstructing of instruction sequence without pipeline interlock. The reconstructed codes can be generated efficiently by considering timing hazard and sequencing hazard simultaneously. And dynamic execution time of program is improved by considering structral hazard which can be existed when pipeline is controlled dynamically.
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