대한전자공학회논문지 (Journal of the Korean Institute of Telematics and Electronics)
- 제24권4호
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- Pages.708-712
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- 1987
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- 1016-135X(pISSN)
CAD에 의한 VLSI 설계를 위한 면적 최적화
Area-Optimization for VLSI by CAD
초록
This paper deals with minimizing layout area of VLSI design. A long wire in a VLSI layout causes delay which can be reduced by using a driver. There can be significant area increase when many drivers are introduced in a layout. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area optimal embeddings for VLSI graphs in rectangles of several aspect ratios.
키워드