대한전자공학회논문지 (Journal of the Korean Institute of Telematics and Electronics)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

$3{\mu}m$ 설계 칫수의 이중금속 CMOS 기술을 이용한 표준셀 라이브러리

A $3{\mu}m$ Standard Cell Library Implemented in Single Poly Double Metal CMOS Technology

  • 박종훈 (연세대학교 전자공학과) ;
  • 박춘성 (연세대학교 전자공학과) ;
  • 김봉열 (연세대학교 전자공학과) ;
  • 이문기 (연세대학교 전자공학과)
  • Park, Jon Hoon (Dept. of Elec. Eng., Yonsei Univ.) ;
  • Park, Chun Seon (Dept. of Elec. Eng., Yonsei Univ.) ;
  • Kim, Bong Yul (Dept. of Elec. Eng., Yonsei Univ.) ;
  • Lee, Moon Key (Dept. of Elec. Eng., Yonsei Univ.)
  • 발행 : 1987.02.01
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초록

This paper describes the CMOS standard cell library implemented in double metal single poly gate process with 3\ulcornerm design rule, and its results of testing. This standard cell library contains total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98\ulcornerm, and width in multiple constant grid of 9 \ulcornerm. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. As the testing results of Ring Oscillator among the cell library, the average delay time for Inverter is 1.05 (ns), and the delay time due to channel routing metal is 0.65(ps)per unit length.

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