대한전자공학회논문지 (Journal of the Korean Institute of Telematics and Electronics)
- 제23권2호
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- Pages.269-277
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- 1986
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- 1016-135X(pISSN)
VLSI의 논리 설계 자동화를 위한 ASM 도표와 SDL
ASM Chart and SDL for VLSI Logic Design Automation
- 조중휘 (한양대학교 전자공학과) ;
- 정정화 (한양대학교 전자공학과)
- Cho, Joung Hwee (Dept. of Elec. Eng., Hanyang Univ.) ;
- Chong, Jung Wha (Dept. of Elec. Eng., Hanyang Univ.)
- 발행 : 1986.02.01
초록
This paper proposes a new algorithmic state machine(ASM) chart and a new hardware description for automatic logic design of VLSI. To describe the behavioral characteristics of the design specification, the conventional ASM chart is modified, and a new hardware description language, SDL, is proposed. The SDL is one-to-one correspondent to the proposed ASM chart symbol, and can be used in a hierachical design of VLSI. As a design example, we obtain a logic circuit diagram of gate lebel utilizing a SDL hardware compiler after drawing an ASM chart and describing in SDL.
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