Journal of the Korean Institute of Telematics and Electronics (대한전자공학회논문지)
- Volume 18 Issue 5
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- Pages.1-9
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- 1981
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- 1016-135X(pISSN)
Charge-coupled analog-to-Digital Converter
전하결합소자를 이용한 Analog-to-Digital 변화기
Abstract
Experimental results on a 4-bit charge-coupled A/D converter are described. Major operations in the successive approximation algorithm are implemented in a monolithic chip, CCADC, which was fabricated usir p-channel CCD technology, with its die size of 4,200 mil2 Typical operating frequency range has been found out to be from 500Hz to 200kHz. In that frequency range, no missing code has been found in the whole signal range of 2.4 volts for ramp signal slewing at 1 LSB/(sampling time). A discussion is made on several layout techniques to conserve the nominal binary ratio of (8:4:2:1) among the areas of four adjacent potential wells (M wells), whose charge storing capacities correspond to each bit magnitude - 3.6 pC, 1.8 pC, 0.9 pC, and 0.45 pC nominal in the order of MSB to the LSB. The effect of 'dump slot', which is responsible for the excessive nonlinearity (2
4-bit 전하결합 A/D 변환기에 대한 실험 결과를 제시하였다. Successive approximation algorithm 에 필요한 대개의 기능을 CCADC(charge coupled A/D converter)라는 mono-lithiic chip으로 실현하였다. CCADC는 P-channel 전하결합소자 제작기술에 의하여 만들어졌으며, Chip면적은 약 4,200
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