EDISON SW 활용 경진대회 논문집 (Proceeding of EDISON Challenge)
- 제5회(2016년)
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- Pages.295-298
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- 2016
Comparison study of the future logic device candidates for under 7nm era
- Park, Junsung (School of Information and Communications, Gwangju Institute of Science and Technology)
- 발행 : 2016.03.22
초록
Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.
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