한국진공학회:학술대회논문집 (Proceedings of the Korean Vacuum Society Conference)
- 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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- Pages.342-343
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- 2012
Comparison of Drain-Induced-Barrier-Lowering (DIBL) Effect by Different Drain Engineering
- Choi, Byoung-Seon (School of Information and Communication Engineering, Sungkyunkwan University) ;
- Choi, Pyung-Ho (School of Information and Communication Engineering, Sungkyunkwan University) ;
- Choi, Byoung-Deog (School of Information and Communication Engineering, Sungkyunkwan University)
- 발행 : 2012.02.08
초록
We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage (