Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2009.07a
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- Pages.91_92
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- 2009
A study on the key Issues for implementing the IEC61850 based Gateway
IEC61850 기반의 Gateway 개발을 위한 이슈에 관한 연구
- Oh, Moo-Nam (U2S) ;
- Lee, Suk-Bea (U2S) ;
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Woo, Chun-Hee
(MyongJi College) ;
- Kim, Jung-Soo (Korea Electric Power Data Network Co., Ltd)
- Published : 2009.07.14
Abstract
As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.
Keywords