Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2008.06a
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- Pages.433-434
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- 2008
An ARM7 Processor Design with Improved Pipeline and Function Blocks
개선된 Pipeline과 기능 블록을 가진 ARM7 Processor 설계
- Cho, Hyun-Woo (Dept. of Electronics Engineering Pusan National University) ;
- Huh, Kyung-Chol (Dept. of Electronics Engineering Pusan National University) ;
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Park, Ju-Sung
(Dept. of Electronics Engineering Pusan National University)
- Published : 2008.06.18
Abstract
In this paper, we present an improved design of the conventional ARM7 processor. It is based on the flip-flop to improve the pipeline performance of the processor. Also for improving the performance, the optimization of functional blocks and a multiplier is carried out. According to the experimental results, the maximum delay-time of functional blocks and the execution cycle of a multiplier is reduced by 33% and 2 cycles compared with a conventional design, respectively. Therefore, it leads to improve an operation speed about 30%.
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