Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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3-way SuperScalar Decoder Design for ARMv7 Core

ARMv7 Core를 위한 3-way SuperScalar Decoder 설계

  • Kim, Hyo-Won (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Kim, In-Soo (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Baek, Chul-Ki (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Min, Hyoung-Bok (School of Information&Communication Engineering, Sungkyunkwan University)
  • 김효원 (성균관대학교 정보통신공학부) ;
  • 김인수 (성균관대학교 정보통신공학부) ;
  • 백철기 (성균관대학교 정보통신공학부) ;
  • 민형복 (성균관대학교 정보통신공학부)
  • Published : 2008.10.23
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Abstract

Further evolutions of technologies and needs of users will make mobile equipments improved. To make this happen, processor's good performance is essential. Hence, This paper propose a reform of Instruction Execute and Instruction Decode of contemporary ARMv7 which needs low-power and has the high performance for a faster processor. The first chapter explains why the performance of a processor has to be upgraded, the second chapter shows current technologies. The third chapter explains about the proposal and illustrates the structure. Finally, in the forth chapter, the conclusion will be made. 3-way Superscalar, that is proposed in this paper, will make designing a faster processor possible. And it will contribute for the advanced performance of mobile equipments.

Keywords