한국산학기술학회:학술대회논문집 (Proceedings of the KAIS Fall Conference)
- 한국산학기술학회 2007년도 추계학술발표논문집
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- Pages.78-80
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- 2007
디지털 회로 검증을 위한 하드웨어 시뮬레이션 시스템 구현에 관한 연구
Study on Implementation of Hardware Simulation System for Verification of Digital Circuit
- Cho, Hyun-Seob (Dept of Digital Broadcast Engineering Chungwoon University) ;
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Oh, Myoung-Kwan
(Dept of Computer Science Hyejeon College)
- 발행 : 2007.11.22
초록
According to the development of VLSI integration technology and getting bigger the circuit size, it is a significant problem to verify systemized circuit. The faster and more accurate verification has very significant meaning in the field of electronic industry because it can yield the product comparably faster and reduce the trial and errors. In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.
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