Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Implementation on the 2D product Iterative decoder using Max- scale architecture

Max-scale 구조를 이용한 2차원 생성코드 반복복호기의 구현

  • Baek, Chang-Hui (Dept. of Electronic Engineering, Chosun University) ;
  • Seong, Hae-Kyung (Hanyang Women's Collage, Dept. of Computer science and Informations Technology) ;
  • Rhee, Kang-Hyeon (Dept. of Electronic Engineering, Chosun University)
  • 백창희 (조선대학교 전자공학과) ;
  • 성해경 (한양여자대학 전산정보계열) ;
  • 이강현 (조선대학교 전자공학과)
  • Published : 2006.06.21
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Abstract

In this paper, We design the high performance 2D product Iterative decoder using three different external value design. We improved the external value operation in two ways to reduce the delay and speed. In this proposed operation, each design has been simulated on Matlab and MaxPlusII, and implemented on the FPGA to measure their performance.

Keywords