Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Hardware Implementation of fast ARIA cipher processor based on pipeline structure

파이프라인 구조 기반의 고속 ARIA 암호 프로세서의 하드웨어 구현

  • Ha, Joon-Soo (Department of Electronic Materials Engineering Kwangwoon University) ;
  • Choi, Hyun-Jun (Department of Electronic Materials Engineering Kwangwoon University) ;
  • Seo, Young-Ho (Department of Information and Communication Engineering Hansung University) ;
  • Kim, Dong-Wook (Department of Electronic Materials Engineering Kwangwoon University)
  • 하준수 (광운대학교 전자재료공학과) ;
  • 최현준 (광운대학교 전자재료공학과) ;
  • 서영호 (한성대학교 정보통신공학과) ;
  • 김동욱 (광운대학교 전자재료공학과)
  • Published : 2006.06.21
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Abstract

This paper presented a hardware implementation of ARIA, which is Korean standard block ciphering algorithm. In this work, we proposed a improved architecture based on pipeline structure and confirmed that the design operates in a clock frequency of 101.7MHz and in throughput of 957Mbps in Xilinx FPGA XCV-1600E.

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