대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2006년도 하계종합학술대회
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- Pages.579-580
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- 2006
낮은 누설전류를 위한 소스/드레인-게이트 비중첩 Nano-CMOS구조 전산모사
Simulation of nonoverlapped source/drain-to-gate Nano-CMOS for low leakage current
- Song, Seung-Hyun (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
- Lee, Kang-Sung (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
- Jeong, Yoon-Ha (Department of Electronic and Electrical Engineering Pohang University of Science and Technology)
- 발행 : 2006.06.21
초록
Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.
키워드