Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2005.11a
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- Pages.1087-1090
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- 2005
The Performance Analysis of Distributed Reorder Buffer Superscalar Processor using Queuing Model
큐잉 모델을 이용한 분산된 리오더 버퍼 수퍼스칼라 프로세서의 성능분석
- Baek, Seock-Kyun (Dept. of Electronic Engineering, Inha University) ;
- Jung, Jin-Ha (Dept. of Electronic Engineering, Inha University) ;
- Shin, Kwang-Sik (Dept. of Electronic Engineering, Inha University) ;
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Choi, Sang-Bang
(Dept. of Electronic Engineering, Inha University)
- Published : 2005.11.26
Abstract
In all contemporary superscalar processors, the result repositories are implemented as the Reorder Buffer(ROB) slots. In such designs, the ROB is a large multi-ported structure. There are several approaches for reducing the ROB complexity in processors. The one technique relies on a distributed implementation that spreads the centralized ROB structure across the function units(FUs). Each distributed component sized to match the FU workload and with one write port and one read port on each component. We are using M/M/1 Queuing theory to determine the number of entries in each ROB component that the performance of processor depends on. Our schemes are evaluated using the simulation of CPU2000 benchmarks.
Keywords