Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A CMOS Analog Front End for a WPAN Zero-IF Receiver

  • Moon, Yeon-Kug (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Seo, Hae-Moon (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Park, Yong-Kuk (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Won, Kwang-Ho (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Lim, Seung-Ok (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Kang, Jeong-Hoon (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Park, Young-Choong (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Yoon, Myung-Hyun (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Yoo, June-Jae (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI)) ;
  • Kim, Seong-Dong (Ubiquitous Computing Research Center, Korea Electronics Technology Institute (KETI))
  • Published : 2005.11.26
Download PDF
⟨ Previous Next ⟩

Abstract

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

Keywords