Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2005.11a
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- Pages.731-734
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- 2005
Design of high speed-low voltage LVDS driver circuit with the novel ESD protection device
새로운 구조의 ESD 보호소자를 내장한 고속-저전압 LVDS Driver 설계
- Lee, Jae-Hyun (Electronic Engineering Seokyeong University) ;
- Kim, Kui-Dong (Electronics and Telecommunications Research Institute) ;
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Kwon, Jong-Ki
(Electronics and Telecommunications Research Institute)
;
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Koo, Yong-Seo
(Electronic Engineering Seokyeong University)
- Published : 2005.11.26
Abstract
In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.
Keywords