Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2004.08c
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- Pages.451-454
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- 2004
A Study On Optimized Technology Mapping for FPGA
- Yi Jae Young (Technical Univ. of Budapest) ;
- Szirmay Laszlo (Technical Univ. of Budapest) ;
- Yi Cheon Hee (Chongju Univ., Dept of Electronic Engineering)
- Published : 2004.08.01
Abstract
We studied on the performance optimized synthesis and mapping of design on to one or more FPGA device. Our multi-phased approach optimized the key parameters that affect performance by adequately modeling the impact on wire length, routability, and performance during technology mapping to produce designs that have high performance and high routability potential.