대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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- Pages.553-556
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- 2004
SoC를 위한 다단 HW/SW 분할 알고리듬
A Multi-Level HW/SW Partitioning Algorithm for SoCs
- Ahn, Byung-Gyu (Dept. of Information & Communications, Hanyang University) ;
- Sihn, Bong-Sik (Dept. of Information & Communications, Hanyang University) ;
- Chong, Jong-Wha (Dept. of Information & Communications, Hanyang University)
- 발행 : 2004.06.01
초록
In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average
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