대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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- Pages.451-454
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- 2004
향상된 재구성능력을 가진 고속 어레이 구조
Fast Array Architecture with Improved Reconfigurability
- Lee Jae-Ic (School of Electronics and Information Kyung Hee University) ;
- Kim Jinsang (School of Electronics and Information Kyung Hee University) ;
- Cho Won-Kyung (School of Electronics and Information Kyung Hee University) ;
- Kim Youngsoo (School of Electronics and Information Kyung Hee University)
- 발행 : 2004.06.01
초록
The reconfigurable architecture is increasingly important for design of multi-mode communication systems and computation-intensive DSP systems. The proposed coarse-grain architecture is based on a reconfigurable processing element consisting of a MAC unit, a register file, a context data register, and PE interconnect control blocks. The main feature of the Proposed architecture is the loop context which enables faster configuration. Also, we propose another area-efficient reconfigurable architecture with improved reconfigurability. The SystemC modeling results show that the proposed architecture can reduce 9 clock cycles of 2D DCT compared to existing architectures.
키워드