한국전기전자재료학회:학술대회논문집 (Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference)
- 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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- Pages.149-153
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- 2003
HSS STI-CMP 공정의 최적화에 관한 연구
Study on the Optimization of HSS STI-CMP Process
- Jeong, So-Young (Dept. of Electrical Eng., Daebul University) ;
- Seo, Yong-Jin (Dept. of Electrical Eng., Daebul University) ;
- Park, Sung-Woo (Dept. of Electrical Eng., Daebul University) ;
- Kim, Chul-Bok (Dongsung A&T) ;
- Kim, Sang-Yong (Dongbu ANAM Fab.) ;
- Lee, Woo-Sun (Chosun University)
- 발행 : 2003.05.16
초록
Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between
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