Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low Complexity GF(2$^{m}$ ) Multiplier based on AOP

회로 복잡도를 개선한 AOP 기반의 GF(2$^{m}$ ) 승산기

  • 변기영 (가톨릭대학교 정보통신전자공학부) ;
  • 성현경 (상지대학교 컴퓨터정보공학부) ;
  • 김흥수 (인하대학교 전자공학과)
  • Published : 2003.07.01
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Abstract

This study focuses on the new hardware design of fast and low-complexity multiplier over GF(2$\^$m/). The proposed multiplier based on the irreducible all one polynomial (AOP) of degree m, to reduced the system's complexity. It composed of Cyclic Shift, Partial Product, and Modular Summation Blocks. Also it consists of (m＋1)$^2$2-input AND gates and m(m＋1) 2-input XOR gates. Out architecture is very regular, modular and therefore, well-suited for VLSI implementation.

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