Design of PCI Express Physical Layer IP

PCI Express 물리계층의 IP 설계

In this paper, we propose design of PCI Express Physical Layer for IP. The proposed design is compatible with PCI Express Base specification Revision 1.0a. and supports only single Lane. The best feature of this design is that Physical Layer includes Power Management block. Therefor, the entire design of PCI Express component is simplified. In the near future, as optimizing this design and extending Lane, we will redesign Physical Layer.