고속 시리얼 데이터 링크용 클럭 및 데이터 복원회로 설계

Design of a Clock and Data Recovery Circuit for High-Speed Serial Data Link Application

This paper proposes a 2x oversampling method with a smart sampling for a clock and data recovery(CDR) circuit in a 2.5Gbps serial data link. In the conventional 2x oversampling method, the "bang-bang" operation of the phase detection produces a systematic jitter in CDR. The smart sampling in phase detection helps the CDR to remove the "bang-bang" operation and to improve the jitter performance. The CDR with the proposed 2x oversampling method is designed using Samsung 0.25${\mu}{\textrm}{m}$ process parameters and verified by simulation. Simulation result shows the proposed 2x oversampling method removes the systematic jitter.e systematic jitter.