A research on an efficient methodology for conversion from Verilog to SystemC

Verilog에서 SystemC로 변환을 위한 효율적인 방법론 연구

Recently, SystemC is one among the language observed. In Industry, there are many the languages that use Verilog. But, unskillful SystemC users must learn SystemC for conversion that from Verilog to SystemC and need time and effort for this. By these reason, feel necessity of easy and efficient conversion. This paper argues efficient methodology to change Verilog to SystemC. Abstract concepts of Verilog are proposed fittingly each one by one in SystemC.