Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2003.07b
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- Pages.787-790
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- 2003
Design of High-Speed Correlator for a Binary CDMA
Binary CDMA를 위한 고속 코릴레이터 설계
Abstract
This paper describes a high speed correlator that can acquire synchronization quickly. The existing addition algorithm is a binary adder tree architecture that will result in extremely slow speed of operation due to many levels of logic required for computation of correlation[2][3]. This paper suggests the new various architectures, which are systolic array architecture, simple pipeline architecture and block systolic array architecture[4][5]. The acquisition performance of the proposed architectures is analyzed and compared with the existing architecture. The comparison results show that the systolic array architecture and the block systolic array architecture reduce the timing delay up to 73% and 31%, respectively. And the results show that the simple pipeline architecture reduces the timing delay up to 53%..
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