한국정보과학회:학술대회논문집 (Proceedings of the Korean Information Science Society Conference)
- 한국정보과학회 2003년도 봄 학술발표논문집 Vol.30 No.1 (B)
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- Pages.283-285
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- 2003
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- 1598-5164(pISSN)
FPGA에서 시간구동 최적화의 배치.배선에 관한 연구
A Study on Place and Route of Time Driven Optimization in the FPGA
- Kim, Hyeonho (Chungbuk Provincial Univ. of Science & Technology, Shinsung College) ;
- Lee, Yonghui (Chungbuk Provincial Univ. of Science & Technology, Shinsung College) ;
- Cheonhee Yi (Chongju Univ.)
- 발행 : 2003.04.01
초록
We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.
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