Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Calculation of Optimum Cell Spacing for Minimum On-resistance of Trench Power MOSFET

Trench Power MOSFET의 최소 on 저항을 위한 cell spacing의 계산

  • 홍지훈 (아주대학교 전자공학과 전자소자연구실) ;
  • 정상구 (아주대학교 전자공학과 전자소자연구실) ;
  • 최연익 (아주대학교 전자공학과 전자소자연구실)
  • Published : 2002.11.09
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Abstract

The trench MOSFET structure is characterized by reduced on-resistance due to elimination of $R_{JFET}$ and high packing density. An analytical calculation of Ron as the sum of $R_{ch}$ and $R_{epi}$ has been reported previously for the trench MOSFET structure. However, the accumulation layer resistance may not be neglected for Trench MOSFET especially for a relatively large value of the cell spacing, where a major contribution to Ron comes from Ra as the simulation results in this paper shows.

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