Hierarchical Timing Analysis considering Global False Path

As the integrated circuit technology gets developed, a circuit size of more than thousands of transistors becomes normal. A hierarchical design is unavoidable due to a huge circuit size. It is important how we can consider hierarchical structure in circuit delay analysis. In this paper we present an accurate method to analyze the delay of circuit with hierarchical structure. Adding the notion of global false path to the hierarchical timing analysis performs more accurate timing analysis.