Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.07b
- /
- Pages.1292-1295
- /
- 2002
A Design of Multiple-Valued Logic Circuits Using Neuron Mos Transister
- Inui, M. (Graduate School of Engineering) ;
- Imai, H. (Graduate School of Engineering) ;
- Harashima, K. (Faculty of Engineering Osaka Institute of Technology) ;
- Kutsuwa, T. (Faculty of Engineering Osaka Institute of Technology)
- Published : 2002.07.01
Abstract
The performance of the LSI improved drastically due to the progress of the semiconductor manufacturing technology in recent years. However, a new problem such as wiring delay and complication inside the LSI occurs. The study to solve these problems with much research organization is been doing. We tried to solve of these problems by using the neuron MOS transistor with 4-valued signal in addition to the binary signal. In this paper, We present, method which realizes 4-valued logic function. And, a designed circuit, is verified by using HSPICE.
Keywords